Design Resources for RiskFive.

This page will provide design resources and files necessary for both hardware and firmware development.


User Constraint Files (UCF).

The User Constraint Files (UCF) for the ABone + Motherboard system are available to download.
Please download the UCF file updated July/24/2018.


ZBT SRAM Reference Designs.

The ZBT SRAM memory Application Notes from both Xilinx and Altera provide good reading material concerning the ZBT memory interfacing. The Xilinx App Note is marked "Under Obsolescence", what does not diminish its educational value. The Verilog and VHDL code archives need a careful revision because they are targeting older versions of Xilinx devices.

Please download Xilinx ZBT application note XAPP136 titled "Synthesizable 200 MHz ZBT SRAM Interface", version 2.0, January 10, 2000.

VHDL code, size 9 kB.

Verilog code, size 13 kB.

Please download Altera ZBT application note AN-329-1.0 titled "ZBT SRAM Controller Reference Design for Stratix & Stratix GX Devices", version 1.0, March 2004.


ZBT SRAM Reference Design from Open Cores.

The Wishbone-compatible non-commercial ZBT SRAM memory controller has been released to Open Cores by Victor Lopez Lorenzo in 2009. The author has simulated and verified the design on a Xilinx Virtex-5 FPGA board ML-506.

Note: Internet Explorer seems to have some problems displaying the Open Cores page. Try Firefox instead.


Please inquire concerning other specs and details that have not been covered above.



Updated July/26/2018.
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