Overview of the RiskX Single Board Computers and Oberon Operating System

Synopsis. The Risk project aims at creation of instruments running the FPGA Oberon System. The instruments will be built around Field Programmable Gate Arrays (FPGA). They will not provide any conventional CPU such as x86 or ARM. The FPGAs will run a real time Oberon operating system with the help of an embedded soft processor core named RISC5.

Motivation. The Oberon System, being real time and small size, is a great candidate for controlling instrumentation. Linux, which is often used for this purpose, has a much larger memory footprint, complexity, sluggish interrupt handling, lack of determinism, and substantial development effort. A much smaller Oberon System can be a better tool for developing efficient low cost instruments.

Background information. The single user workstation Oberon System was originally developed in mid 1980's. A new edition of this OS was released by Professor Niklaus Wirth and Paul Reed in 2013 for the Spartan-3 FPGA. Since then several implementations were developed for Spartan-6, Spartan-7, and Artix-7. The same FPGA Oberon System is also running under emulated FPGA environments on a PC. Please check the Web resources page for more information.

The original Oberon System was a complete workstation with its own GUI, keyboard, mouse, and a disk file system. It ran on an academic 32-bit machine with 2 MB of dynamic RAM and 256 kB of video RAM. It used a 32-bit processor NS32032 clocked at 10 MHz. The system could self-compile itself. The same is now true under the 2013 FPGA Oberon System. Cross development is also supported. Several PC-based emulators are available where one can cross develop software and download it to the board for execution.

Hardware, firmware, software. The FPGA Oberon System needs a hardware board with a sufficiently large FPGA for hosting its firmware, whose primary component is the RISC5 soft processor core running the Oberon System software. There are Oberon projects out there which rely solely on the third party boards (e.g., Astrobe). We have chosen to develop our own boards in order to future proof the project against the third party boards being pulled out of market.

Customizable general purpose computer. The FPGA Oberon System is a general purpose computer which can be customized to a particular application. The customization can be either in software, firmware, or both. Firmware is adding a new dimension to customization. The computer can be augmented with coprocessors, state machines, streaming interfaces, or custom peripherals. Firmware customization is outside the realm of conventional single board computers such as Arduino or Raspberry Pi.

Applications. We plan to use the Oberon System to develop reliable embedded software for instrumentation. We plan to adopt both the Workstation and the Embedded variants for this purpose (explained below).

There are two major variants of the FPGA Oberon System. The Workstation Oberon System can be used for in situ software development, using the workstation itself. The diagram shows the major components of the workstation. Not all of them have to be present. The minimal configuration comprises the solid state disk (i.e., the SD card), mouse, keyboard, and video monitor display. The workstation software comprises the compiler, loader, run time system, device drivers, and the graphical user interface. The workstion can run with a single megabyte of RAM.

The Deeply Embedded Oberon System (DEOS) cannot be used for self development because it lacks the video, mouse, keyboard, and the on board compiler. Software is rather developed under a cross development environment running on a PC. Astrobe is an example of such an environment. The embedded Oberon System can run in kilobytes rather than megabytes, using the on-chip Block RAM (BRAM) for execution. The software is downloaded and controlled using a serial cable. Other components can be present as well, such as Ethernet or wireless.

The Minimal Embedded Oberon System (MEOS) goes one step further in hardware integration. The Oberon System Disk can be moved into the FPGA boot flash to avoid using a separate SD card. The file system will then use the extra space left over in the FPGA flash, beyond the area utilized by the FPGA bit image. MEOS is taking advantage of the resources which are already present on board. Other components can be present as well, such as Ethernet or wireless. MEOS development will require porting the existing SD card driver to support the NOR flash instead of the SD card.

It is notable that the FPGA is the only major logic on the Oberon boards. There is not even a trace of the conventional CPU other than the FPGA itself. The entire operating system is executed by the RISC5 soft core inside the FPGA.

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Updated June/17/2020.
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