RISC5 Soft Processor Core

Synopsis. FPGA Oberon System is running on a soft processor core named RISC5. In this section I will summarize the main features of this core.

Motivation. The authors of the 2013 FPGA Oberon System developed the RISC5 core to provide a complete implementation of the computer running their software operating system. The core could be instantiated in any FPGA, providing a layer of safety against hardware obsolescence. The core was written in Verilog and it was deliberately very simple. It was upgraded in 2018 with interrupt processing, which was lacking in the original 2013 version.

Background information. The step-wise development of RISC5 is documented on a N.Wirth's personal website in a comprehensive paper The Design of a RISC Architecture and its Implementation with an FPGA. A concise 3-page summary is presented in another paper titled The RISC Architecture. The latest modifications were described in the third paper, wisely hidden in another directory where it may be hard to find. All three papers provide many details which were not included in the "official" e-book on Oberon System available from the same website.

Concise overview of both the core and the software. Niklaus Wirth published a concise article Oberon System Implemented on a Low-Cost FPGA Board (Issue 91, page 30, Second Quarter 2015, Xilinx's Xcell Journal). The article is describing both the RISC5 core and the 2013 FPGA Oberon System implementation running on the Digilent Spartan-3 Starter Kit.

RISC5 versus RISC-V. RISC5 has absolutely nothing to do with RISC-V, which is a completely separate soft core originating from Berkeley. RISC5 is intentionally simple, what cannot be said about RISC-V. On the other hand, Oberon compilers for RISC-V exist and are in active development.

Summary. The N.Wirth's personal website provides lots of information which every Oberon developer needs to study in detail. All directories of this website provide hidden gems of documentation. It is sometimes surprising, which information was provided where on that website. The architecture of the RISC5 core is described in great detail in at least three papers, in addition to the e-book on the Oberon System proper. RISC5 has absolutely nothing to do with RISC-V.

Verilog code size and Instruction Set Architecture (ISA). RISC5 is deliberately very simple and of small size. Its core Verilog modules consist of only 438 code lines of Verilog. The core features only 20 instructions: four for moving, shifting and rotating; four for logic operations; four for integer arithmetic; four for floating- point arithmetic; two for memory access; and two for branching. Such a simple structure was carefully crafted to enable efficient compilation and good performance of Oberon programs.

Carefully tuned features. The RISC5 ISA was tailored to run the Oberon operating system consisting of the run time system, device drivers, high level Oberon language compiler, and graphical user interface. Since both the OS and the soft CPU were designed hand-in-hand, there was virtually nothing which could be called "unnecessary" in the design of either piece. Other popular cores like ARM or RISC-V include many features which are necessary to run a protected operating system like Linux. Such features are hardly needed to run the Oberon System.

Oberon System-on-Chip (SoC). RISC5 core was surrounded with a small set of peripherals turning it into a System-on-Chip workstation with 1 MB of RAM, keyboard, mouse, graphics display, wireless network, and SD card for file storage. The SoC took 95.4% of the Spartan-3 chip XC3S200 for which it was originally developed.

Porting the Oberon SoC to other FPGAs. According to the FPGA compilation reports, the entire SoC occupies about half of the second-smallest Spartan-6 XC6SLX9, and only 4% of the largest Spartan-6 XC6SLX150. It takes only 3% of the largest Artix-7 XC7A200T. All these FPGAs are considerd "cost optimized" by Xilinx. (The XC6SLX9 costs only $16 when purchased in small numbers from DigiKey.) These are the chips of choice for designing low cost, power efficient instruments such as Edge Devices or Internet of Things.

Performance. While there is no lowest speed limit at which RISC5 can run (it can be kHz), the RISC5 upper speed limit depends on two separate factors. The original design could be reliably clocked at 25 MHz on the Spartan-3 Starter Kit featuring the asynchronous RAM, which is notoriously difficult to interface with. Professor Pong P. Chu devoted an entire chapter in his book FPGA Prototyping book (Spartan-3 Version) to this particular ASRAM chip on this particular board. His conclusions were similar to Wirth's. It is thus no wonder that the Oberon SoC could run at only 25 MHz with this kind of memory. (To be quite honest, Magnus Karlsson achieved a higher speed on his Pepino board using the same ASRAM chip.) A separate limitation comes from the internal architecture of RISC5 which is heavily combinatorial with little pipelining. I believe that the Oberon SoC can eventually run much faster after switching to a faster kind of memory (ZBT rather than ASRAM) and after pipelining the RISC5 Verilog design.

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Updated June/13/2020.
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