Device Usage Page (usage_statistics_webtalk.html)

This HTML page displays the device usage statistics that will be sent to Xilinx.
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software_version_and_target_device
betaFALSE build_version2405991
date_generatedThu Dec 19 12:29:23 2019 os_platformWIN64
product_versionVivado v2018.3 (64-bit) project_id784b115ce62f4193925a2a92e01833be
project_iteration93 random_id174554af17695a1e95fdb73f02a20198
registration_id211429644_1777532096_0_348 route_designTRUE
target_devicexc7a35t target_familyartix7
target_packagecsg324 target_speed-1
tool_flowVivado

user_environment
cpu_nameIntel(R) Core(TM) i5 CPU 650 @ 3.20GHz cpu_speed3192 MHz
os_nameMicrosoft Windows 8 or later , 64-bit os_releasemajor release (build 9200)
system_ram8.000 GB total_processors1

vivado_usage
gui_handlers
abstractcombinedpanel_remove_selected_elements=1 addilaprobespopup_cancel=1 addilaprobespopup_ok=1 addsrcwizard_specify_hdl_netlist_block_design=5
addsrcwizard_specify_or_create_constraint_files=3 basedialog_cancel=129 basedialog_ok=104 cmdmsgdialog_ok=29
confirmsavetexteditsdialog_cancel=1 confirmsavetexteditsdialog_no=2 constraintschooserpanel_add_files=4 constraintschooserpanel_create_file=2
constraintschooserpanel_file_table=1 coretreetablepanel_core_tree_table=18 createconstraintsfilepanel_file_name=1 createsrcfiledialog_file_name=1
designtimingsumsectionpanel_worst_negative_slack=1 editprobevaluedialog_cancel=2 editprobevaluedialog_ok=1 expreporttreepanel_exp_report_tree_table=3
expruntreepanel_exp_run_tree_table=6 filesetpanel_file_set_panel_tree=506 flownavigatortreepanel_flow_navigator_tree=1297 flownavigatortreepanel_open=2
hacgcipsymbol_show_disabled_ports=4 hardwareilawaveformview_run_trigger_for_this_ila_core=374 hardwareilawaveformview_stop_trigger_for_this_ila_core=68 hardwareilawaveformview_toggle_auto_re_trigger_mode=4
hardwaretreepanel_hardware_tree_table=5 hcodeeditor_search_text_combo_box=1 hjfilechooserhelpers_jump_to_current_working_directory=7 hjfilechooserrecentlistpreview_recent_directories=1
hpopuptitle_close=6 ilaprobetablepanel_add_probe=102 ilaprobetablepanel_add_probes=1 ilaprobetablepanel_remove_selected_probe=73
ilaprobetablepanel_set_trigger_condition_to_global=1 mainmenumgr_file=4 maintoolbarmgr_run=1 msgtreepanel_discard_user_created_messages=9
msgtreepanel_message_severity=11 msgtreepanel_message_view_tree=85 msgview_critical_warnings=5 msgview_error_messages=2
msgview_information_messages=4 msgview_warning_messages=4 navigabletimingreporttab_timing_report_navigation_tree=24 openfileaction_open_directory=1
pacommandnames_add_sources=9 pacommandnames_auto_connect_target=19 pacommandnames_auto_update_hier=5 pacommandnames_create_user_defined_debug_probe=2
pacommandnames_edit_simulation_sets=1 pacommandnames_impl_settings=1 pacommandnames_new_project=1 pacommandnames_open_hardware_manager=1
pacommandnames_open_target_wizard=1 pacommandnames_run_trigger=7 pacommandnames_src_disable=5 pacommandnames_src_enable=1
pacommandnames_src_replace_file=1 pacommandnames_stop_trigger=1 pacommandnames_unmark_all=2 partchooser_family_chooser=1
partchooser_part_package_chooser=1 partchooser_part_speed_chooser=1 partchooser_parts=3 pathreporttableview_description=7
paviews_code=9 paviews_dashboard=39 paviews_ip_catalog=1 paviews_package=1
paviews_par_report=1 paviews_project_summary=22 probesview_probes_tree=134 probevaluetablepanel_probe_bit_position_table=1
probevaluetablepanel_text_field=244 programfpgadialog_program=551 programfpgadialog_specify_bitstream_file=51 programfpgadialog_specify_debug_probes_file=2
progressdialog_background=6 progressdialog_cancel=6 projecttab_close_design=1 projecttab_reload=1
rdicommands_cut=1 rdicommands_delete=5 rdicommands_line_comment=4 rdicommands_properties=4
rdicommands_save_all_files=1 rdicommands_save_file=14 rdicommands_settings=1 rdiviews_waveform_viewer=2942
saveprojectutils_cancel=1 saveprojectutils_save=3 settingsdialog_options_tree=13 settingsdialog_project_tree=19
settingsprojectgeneralpage_choose_device_for_your_project=1 simpleoutputproductdialog_generate_output_products_immediately=14 srcchooserpanel_add_hdl_and_netlist_files_to_your_project=9 srcchooserpanel_create_file=1
srcchoosertable_src_chooser_table=1 srcmenu_ip_documentation=3 srcmenu_ip_hierarchy=6 srcmenu_open_selected_source_files=1
srcmenu_refresh_hierarchy=1 statemonitor_reset_run=2 syntheticastatemonitor_cancel=8 tclconsoleview_tcl_console_code_editor=3
timingitemflattablepanel_table=62 triggersetuppanel_table=813 triggerstatuspanel_run_trigger_for_this_ila_core=61 triggerstatuspanel_stop_trigger_for_this_ila_core=24
waveformnametree_waveform_name_tree=266 waveformview_add=28 xdcviewertreetablepanel_xdc_viewer_tree_table=1
java_command_handlers
addcfgmem=11 addsources=9 autoconnecttarget=17 coreview=5
createuserdefinedprobe=2 customizecore=4 editdelete=5 editpaste=1
editproperties=3 editsimulationsets=1 editundo=2 launchopentarget=1
launchprogramfpga=568 newproject=1 openhardwaredashboard=1 openhardwaremanager=592
openrecenttarget=42 programdevice=627 recustomizecore=15 reporttimingsummary=4
runbitgen=123 runtrigger=428 saveallfiles=1 savefileproxyhandler=9
setsourceenabled=6 showview=1 stoptrigger=95 timingconstraintswizard=2
toolssettings=7 unselectallcmdhandler=1 viewlayoutcmd=1 viewtaskimplementation=4
viewtaskprogramanddebug=16 viewtaskprojectmanager=64
other_data
guimode=18
project_data
constraintsetcount=1 core_container=false currentimplrun=impl_1 currentsynthesisrun=synth_1
default_library=xil_defaultlib designmode=RTL export_simulation_activehdl=12 export_simulation_ies=12
export_simulation_modelsim=12 export_simulation_questa=12 export_simulation_riviera=12 export_simulation_vcs=12
export_simulation_xsim=12 implstrategy=Vivado Implementation Defaults launch_simulation_activehdl=0 launch_simulation_ies=0
launch_simulation_modelsim=0 launch_simulation_questa=0 launch_simulation_riviera=0 launch_simulation_vcs=0
launch_simulation_xsim=0 simulator_language=Mixed srcsetcount=19 synthesisstrategy=Vivado Synthesis Defaults
target_language=Verilog target_simulator=XSim totalimplruns=2 totalsynthesisruns=2

unisim_transformation
post_unisim_transformation
bufg=5 carry4=162 fdre=812 fdse=72
gnd=17 ibuf=41 ldce=32 lut1=151
lut2=134 lut3=453 lut4=305 lut5=402
lut6=1268 mmcme2_adv=1 muxf7=82 obuf=63
obuft=34 ramd32=108 rams32=36 vcc=17
pre_unisim_transformation
bufg=5 carry4=162 fdre=812 fdse=72
gnd=17 ibuf=7 iobuf=34 ldce=32
lut1=151 lut2=134 lut3=453 lut4=305
lut5=402 lut6=1268 mmcme2_adv=1 muxf7=82
obuf=63 ram32m=18 vcc=17

report_drc
command_line_options
-append=default::[not_specified] -checks=default::[not_specified] -fail_on=default::[not_specified] -force=default::[not_specified]
-format=default::[not_specified] -internal=default::[not_specified] -internal_only=default::[not_specified] -messages=default::[not_specified]
-name=default::[not_specified] -no_waivers=default::[not_specified] -return_string=default::[not_specified] -ruledecks=default::[not_specified]
-upgrade_cw=default::[not_specified] -waived=default::[not_specified]
results
cfgbvs-1=1

report_methodology
command_line_options
-append=default::[not_specified] -checks=default::[not_specified] -fail_on=default::[not_specified] -force=default::[not_specified]
-format=default::[not_specified] -messages=default::[not_specified] -name=default::[not_specified] -return_string=default::[not_specified]
-slack_lesser_than=default::[not_specified] -waived=default::[not_specified]
results
timing-16=54 timing-18=19 timing-20=32

report_power
command_line_options
-advisory=default::[not_specified] -append=default::[not_specified] -file=[specified] -format=default::text
-hier=default::power -hierarchical_depth=default::4 -l=default::[not_specified] -name=default::[not_specified]
-no_propagation=default::[not_specified] -return_string=default::[not_specified] -rpx=[specified] -verbose=default::[not_specified]
-vid=default::[not_specified] -xpe=default::[not_specified]
usage
airflow=250 (LFM) ambient_temp=25.0 (C) bi-dir_toggle=12.500000 bidir_output_enable=1.000000
board_layers=12to15 (12 to 15 Layers) board_selection=medium (10"x10") clocks=0.006300 confidence_level_clock_activity=High
confidence_level_design_state=High confidence_level_device_models=High confidence_level_internal_activity=Medium confidence_level_io_activity=Low
confidence_level_overall=Low customer=TBD customer_class=TBD devstatic=0.071997
die=xc7a35tcsg324-1 dsp_output_toggle=12.500000 dynamic=0.148322 effective_thetaja=4.8
enable_probability=0.990000 family=artix7 ff_toggle=12.500000 flow_state=routed
heatsink=medium (Medium Profile) i/o=0.049777 input_toggle=12.500000 junction_temp=26.1 (C)
logic=0.003234 mgtavcc_dynamic_current=0.000000 mgtavcc_static_current=0.000000 mgtavcc_total_current=0.000000
mgtavcc_voltage=1.000000 mgtavtt_dynamic_current=0.000000 mgtavtt_static_current=0.000000 mgtavtt_total_current=0.000000
mgtavtt_voltage=1.200000 mmcm=0.085414 netlist_net_matched=NA off-chip_power=0.000000
on-chip_power=0.220319 output_enable=1.000000 output_load=5.000000 output_toggle=12.500000
package=csg324 pct_clock_constrained=6.000000 pct_inputs_defined=2 platform=nt64
process=typical ram_enable=50.000000 ram_write=50.000000 read_saif=False
set/reset_probability=0.000000 signal_rate=False signals=0.003597 simulation_file=None
speedgrade=-1 static_prob=False temp_grade=commercial thetajb=6.8 (C/W)
thetasa=4.6 (C/W) toggle_rate=False user_board_temp=25.0 (C) user_effective_thetaja=4.8
user_junc_temp=26.1 (C) user_thetajb=6.8 (C/W) user_thetasa=4.6 (C/W) vccadc_dynamic_current=0.000000
vccadc_static_current=0.020000 vccadc_total_current=0.020000 vccadc_voltage=1.800000 vccaux_dynamic_current=0.048665
vccaux_io_dynamic_current=0.000000 vccaux_io_static_current=0.000000 vccaux_io_total_current=0.000000 vccaux_io_voltage=1.800000
vccaux_static_current=0.012633 vccaux_total_current=0.061298 vccaux_voltage=1.800000 vccbram_dynamic_current=0.000000
vccbram_static_current=0.000165 vccbram_total_current=0.000165 vccbram_voltage=1.000000 vccint_dynamic_current=0.014269
vccint_static_current=0.009792 vccint_total_current=0.024061 vccint_voltage=1.000000 vcco12_dynamic_current=0.000000
vcco12_static_current=0.000000 vcco12_total_current=0.000000 vcco12_voltage=1.200000 vcco135_dynamic_current=0.000000
vcco135_static_current=0.000000 vcco135_total_current=0.000000 vcco135_voltage=1.350000 vcco15_dynamic_current=0.000000
vcco15_static_current=0.000000 vcco15_total_current=0.000000 vcco15_voltage=1.500000 vcco18_dynamic_current=0.000000
vcco18_static_current=0.000000 vcco18_total_current=0.000000 vcco18_voltage=1.800000 vcco25_dynamic_current=0.000000
vcco25_static_current=0.000000 vcco25_total_current=0.000000 vcco25_voltage=2.500000 vcco33_dynamic_current=0.014078
vcco33_static_current=0.001000 vcco33_total_current=0.015078 vcco33_voltage=3.300000 version=2018.3

report_utilization
clocking
bufgctrl_available=32 bufgctrl_fixed=0 bufgctrl_used=5 bufgctrl_util_percentage=15.63
bufhce_available=72 bufhce_fixed=0 bufhce_used=0 bufhce_util_percentage=0.00
bufio_available=20 bufio_fixed=0 bufio_used=0 bufio_util_percentage=0.00
bufmrce_available=10 bufmrce_fixed=0 bufmrce_used=0 bufmrce_util_percentage=0.00
bufr_available=20 bufr_fixed=0 bufr_used=0 bufr_util_percentage=0.00
mmcme2_adv_available=5 mmcme2_adv_fixed=0 mmcme2_adv_used=1 mmcme2_adv_util_percentage=20.00
plle2_adv_available=5 plle2_adv_fixed=0 plle2_adv_used=0 plle2_adv_util_percentage=0.00
dsp
dsps_available=90 dsps_fixed=0 dsps_used=0 dsps_util_percentage=0.00
io_standard
blvds_25=0 diff_hstl_i=0 diff_hstl_i_18=0 diff_hstl_ii=0
diff_hstl_ii_18=0 diff_hsul_12=0 diff_mobile_ddr=0 diff_sstl135=0
diff_sstl135_r=0 diff_sstl15=0 diff_sstl15_r=0 diff_sstl18_i=0
diff_sstl18_ii=0 hstl_i=0 hstl_i_18=0 hstl_ii=0
hstl_ii_18=0 hsul_12=0 lvcmos12=0 lvcmos15=0
lvcmos18=0 lvcmos25=0 lvcmos33=1 lvds_25=0
lvttl=0 mini_lvds_25=0 mobile_ddr=0 pci33_3=0
ppds_25=0 rsds_25=0 sstl135=0 sstl135_r=0
sstl15=0 sstl15_r=0 sstl18_i=0 sstl18_ii=0
tmds_33=0
memory
block_ram_tile_available=50 block_ram_tile_fixed=0 block_ram_tile_used=0 block_ram_tile_util_percentage=0.00
ramb18_available=100 ramb18_fixed=0 ramb18_used=0 ramb18_util_percentage=0.00
ramb36_fifo_available=50 ramb36_fifo_fixed=0 ramb36_fifo_used=0 ramb36_fifo_util_percentage=0.00
primitives
bufg_functional_category=Clock bufg_used=5 carry4_functional_category=CarryLogic carry4_used=162
fdre_functional_category=Flop & Latch fdre_used=813 fdse_functional_category=Flop & Latch fdse_used=72
ibuf_functional_category=IO ibuf_used=41 ldce_functional_category=Flop & Latch ldce_used=32
lut1_functional_category=LUT lut1_used=144 lut2_functional_category=LUT lut2_used=134
lut3_functional_category=LUT lut3_used=453 lut4_functional_category=LUT lut4_used=305
lut5_functional_category=LUT lut5_used=402 lut6_functional_category=LUT lut6_used=1268
mmcme2_adv_functional_category=Clock mmcme2_adv_used=1 muxf7_functional_category=MuxFx muxf7_used=82
obuf_functional_category=IO obuf_used=63 obuft_functional_category=IO obuft_used=34
ramd32_functional_category=Distributed Memory ramd32_used=108 rams32_functional_category=Distributed Memory rams32_used=36
slice_logic
f7_muxes_available=16300 f7_muxes_fixed=0 f7_muxes_used=82 f7_muxes_util_percentage=0.50
f8_muxes_available=8150 f8_muxes_fixed=0 f8_muxes_used=0 f8_muxes_util_percentage=0.00
lut_as_distributed_ram_fixed=0 lut_as_distributed_ram_used=72 lut_as_logic_available=20800 lut_as_logic_fixed=0
lut_as_logic_used=2366 lut_as_logic_util_percentage=11.38 lut_as_memory_available=9600 lut_as_memory_fixed=0
lut_as_memory_used=72 lut_as_memory_util_percentage=0.75 lut_as_shift_register_fixed=0 lut_as_shift_register_used=0
register_as_flip_flop_available=41600 register_as_flip_flop_fixed=0 register_as_flip_flop_used=885 register_as_flip_flop_util_percentage=2.13
register_as_latch_available=41600 register_as_latch_fixed=0 register_as_latch_used=32 register_as_latch_util_percentage=0.08
slice_luts_available=20800 slice_luts_fixed=0 slice_luts_used=2438 slice_luts_util_percentage=11.72
slice_registers_available=41600 slice_registers_fixed=0 slice_registers_used=917 slice_registers_util_percentage=2.20
lut_as_distributed_ram_fixed=0 lut_as_distributed_ram_used=72 lut_as_logic_available=20800 lut_as_logic_fixed=0
lut_as_logic_used=2366 lut_as_logic_util_percentage=11.38 lut_as_memory_available=9600 lut_as_memory_fixed=0
lut_as_memory_used=72 lut_as_memory_util_percentage=0.75 lut_as_shift_register_fixed=0 lut_as_shift_register_used=0
lut_in_front_of_the_register_is_unused_fixed=0 lut_in_front_of_the_register_is_unused_used=80 lut_in_front_of_the_register_is_used_fixed=80 lut_in_front_of_the_register_is_used_used=185
register_driven_from_outside_the_slice_fixed=185 register_driven_from_outside_the_slice_used=265 register_driven_from_within_the_slice_fixed=265 register_driven_from_within_the_slice_used=652
slice_available=8150 slice_fixed=0 slice_registers_available=41600 slice_registers_fixed=0
slice_registers_used=917 slice_registers_util_percentage=2.20 slice_used=709 slice_util_percentage=8.70
slicel_fixed=0 slicel_used=492 slicem_fixed=0 slicem_used=217
unique_control_sets_available=8150 unique_control_sets_fixed=8150 unique_control_sets_used=41 unique_control_sets_util_percentage=0.50
using_o5_and_o6_fixed=0.50 using_o5_and_o6_used=72 using_o5_output_only_fixed=72 using_o5_output_only_used=0
using_o6_output_only_fixed=0 using_o6_output_only_used=0
specific_feature
bscane2_available=4 bscane2_fixed=0 bscane2_used=0 bscane2_util_percentage=0.00
capturee2_available=1 capturee2_fixed=0 capturee2_used=0 capturee2_util_percentage=0.00
dna_port_available=1 dna_port_fixed=0 dna_port_used=0 dna_port_util_percentage=0.00
efuse_usr_available=1 efuse_usr_fixed=0 efuse_usr_used=0 efuse_usr_util_percentage=0.00
frame_ecce2_available=1 frame_ecce2_fixed=0 frame_ecce2_used=0 frame_ecce2_util_percentage=0.00
icape2_available=2 icape2_fixed=0 icape2_used=0 icape2_util_percentage=0.00
pcie_2_1_available=1 pcie_2_1_fixed=0 pcie_2_1_used=0 pcie_2_1_util_percentage=0.00
startupe2_available=1 startupe2_fixed=0 startupe2_used=0 startupe2_util_percentage=0.00
xadc_available=1 xadc_fixed=0 xadc_used=0 xadc_util_percentage=0.00

synthesis
command_line_options
-assert=default::[not_specified] -bufg=default::12 -cascade_dsp=default::auto -constrset=default::[not_specified]
-control_set_opt_threshold=default::auto -directive=default::default -fanout_limit=default::10000 -flatten_hierarchy=default::rebuilt
-fsm_extraction=default::auto -gated_clock_conversion=default::off -generic=default::[not_specified] -include_dirs=default::[not_specified]
-keep_equivalent_registers=default::[not_specified] -max_bram=default::-1 -max_bram_cascade_height=default::-1 -max_dsp=default::-1
-max_uram=default::-1 -max_uram_cascade_height=default::-1 -mode=default::default -name=default::[not_specified]
-no_lc=default::[not_specified] -no_srlextract=default::[not_specified] -no_timing_driven=default::[not_specified] -part=xc7a35tcsg324-1
-resource_sharing=default::auto -retiming=default::[not_specified] -rtl=default::[not_specified] -rtl_skip_constraints=default::[not_specified]
-rtl_skip_ip=default::[not_specified] -seu_protect=default::none -sfcu=default::[not_specified] -shreg_min_size=default::3
-top=RISC5Top -verilog_define=default::[not_specified]
usage
elapsed=00:02:22s hls_ip=0 memory_gain=645.207MB memory_peak=896.715MB