Using Interrupts in Oberon System Instrumentation

Synopsis. Interrupts help in achieving high performance of real time instrumentation. In this section I will outline how the Oberon System is making use of this essential feature.

Motivation. In the field of Nuclear Electronics, the "events" are generated at random instances by the nuclear decays. The Data Acquisition instruments (DAQ) must catch the decay event quickly enough in order not to miss the next one. Since the event can arrive at any time, periodic process scheduling is not well suited to random event processing. The time-honored interrupts are the proper solution in this case. Fortunately, the 2018 edition of the RISC5 processor is equipped with a simple yet effective provision for interrupt processing.

Background information. About twenty years ago I dealt with the Digital Signal Processor ADSP-2183 by Analog Devices. Upon the interrupt, the chip could switch the context in a single clock cycle. Clocked at 40 MHz, the interrupt service routine (ISR) was entered in less than 100 ns. This kind of rapid response is needed for event processing in Nuclear Physics.

Since then, substantial progress has been achieved by the semiconductor and programming industries. We now use the Texas Instruments AM3558 with ARM Cortex-A8. This powerful chip, clocked at 720 MHz and running Linux, can enter the ISR in about 12.5 microseconds with five microseconds jitter. The TI Wiki with these numbers will only be available till December 2020. Download the content if you want to preserve these numbers.

The progress over these 20 years amounts to increasing (i.e., worsening) the real time interrupt latency by a factor of about 10, despite improving the clock speed about 20 times. The performance deterioration by about two orders of magnitude after factoring in the clock is providing an example of the Wirth's Law discussed in Wikipedia: Software is getting slower more rapidly than hardware is becoming faster. As stated in that article, "What Intel giveth, Microsoft taketh away", even though in this case Intel is ARM, while Microsoft is Linux. Taken together, the lesson seems to be that powerful chips running powerful "industry standard software" are not the best avenue to building efficient data acquisition instrumentation.

Linux interrupt documentation. Quite fortunately, Linux interrupt documentation is a very powerful deterrent against trying to use this technology. Studying "upper halves", "lower halves", tasklets, or work queues provides sufficient motivation to stay away from these topics.

Regaining the interrupt performance. The 2018 edition of the RISC5 processor is equipped with the interrupt circuit with latency of 3 clock cycles, which is below 100 ns if the core is clocked at 50 MHz. Like everything else in Oberon System, the interrupt handler is written in the high level language without the need for assembly coding. This arrangement seems ideal for writing efficient and robust real time code.

As an example, the following very simple ISR is activated by the millisecond clock ticker. It is turning one of the LEDs on and off every half a second.

    PROCEDURE* Int; (*interrupt handler called every millisecond*)
    BEGIN INC(cnt);
    IF cnt = 500 THEN led := 3 - led; LED(led); cnt := 0 END
    END Int;

Summary. Interrupts used to be an essential service available to the programmer, until the situation has been so vastly improved in the "industry standard software" that the interrupts now look like adding an air conditioner to a bicycle. On the other hand, Oberon System is a small system with predictable timing. Its interrupt machinery is both frugal and very efficient. It opens the door to a well performing instrument developed with a very reasonable programming effort.



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Updated June/06/2020.
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