Firmware for RiskFive: Oberon System On Chip.

Similar to the FPro system, the FPGA Oberon Project, Revised Edition 2013 is also a book accompanied by a website. Unlike FPro, the main focus of the Oberon System is on software, while the FPGA is serving merely as a vehicle for running this operating system.

The collection of the firmware cores provided by the Oberon website is similar to the FPro collection, with the important difference that only one System On Chip (SOC) is fully developed in the Oberon Project. The SOC is targeting the Digilent Spartan-3 development board, which was state of the art in 2013, but it is obsolete by today standards. Several cores are provided in source, such as SPI, UART, or PS/2 interface. A very simple video controller is "stealing the cycles" from the system bus. The RISC5 soft processor core was developed to enable running the Oberon Operating system and the Oberon compiler. The entire project is also documented on Wikipedia.

The FPGA Oberon cores were originally written in LoLa Hardware Description Language and then translated to Verilog using the LoLa to Verilog translator. The sources of the cores are remarkably compact. Comments are frugal because the cores are thoroughly discussed in Chapters 16 and 17 of the Oberon book (the upper-right link on the website).

It is hard not to notice that the Oberon System firmware was developed as an "necessary evil" in order to support the Oberon Operating System which was the main focus of the book. The emphasis is evident from the fact that the OS, the compiler, and the software applications are described first, while the entire firmware, including the soft CPU, is described in the last two chapters of the book.

The Oberon System book is remarkably clear. It was first printed in early 1990's by the ACM Press, and then revised and electronically released in 2013. Several other books were devoted to the same subject, including Programming in Oberon: Steps Beyond Pascal and Modula by Reiser and Wirth, as well as the The Oberon System: User Guide and Programmer's Manual by Reiser.

In addition to the original Oberon System by Wirth and Gutknecht, RISC5 is also supported by a commercial software development environment Astrobe. It is remarkable that the RISC5 core is supported for free.

Compared with the FPro project, where the firmware was very strong and the software was rudimentary, the Oberon situation is exactly the opposite. The software is strong, while the firmware seems to serve as merely a demonstration.

I conclude this short section by stressing that the Oberon System and the Oberon compiler are perhaps the only examples how a nontrivial and useful software can run on a very modest FPGA, using a very simple, yet remarkably capable soft core developed specifically for this purpose.

We consider the Oberon language, the RISC5 compiler, and the Oberon Operating System as our prime candidates for the RiskFive software. Thorough documentation, clearly defined rules, and well structured software code are the main assets of the Oberon approach. Concerning the performance, the Spartan-3 version ran at only 25 MHz due to the RAM speed limitations. We expect RISC5 to reach about 100 MHz mark in the high performance DDR3 environment.

The main challenge of the Oberon approach will consist of implementing the RISC5 core under the non-Oberon firmware framework such as either FPro or Wishbone.

Please inquire concerning the details that have not been covered above. Our contact information is listed on the contact page.

Updated Jan/26/2018.
© 2018 by