Firmware for RiskFive: FPro System On Chip.

The book FPGA Prototyping by VHDL Examples, 2nd edition, is accompanied by a comprehensive companion website. Several valuable firmware cores are provided in source, such as SPI, I2C, UART, or PS/2 interface. In adition to these simple cores, the book describes several video controllers of various levels of complexity. The MicroBlaze soft processor core, which is not provided in source by Xilinx, can be instantiated and interfaced with the rest of the firmware using an interface "wrapper" described in the book and provided on the website.

The FPro cores are written in VHDL. The Verilog version of the book is scheduled to appear in Spring 2018. The sources of the cores are remarkably compact. Comments are frugal because the cores are thoroughly discussed in the main text of the book.

Both the simple and advanced cores can be connected to a 32-bit communication bus named FPro (a shorthand for FPGA Prototyping). The bus signals and the rules for interfacing are thoroughly discussed and documented in the book.

It is well known that system integration (i.e., composition from individual modules) is the most challenging part of any nontrivial design. The FPro textbook provides several well documented designs of complete systems composed of various IP cores interconnected by a common bus. The Systems On Chip (SOC) described in the book can be used to kick start a variety of other designs by changing the cores, adding new ones, or interfacing the cores to external devices.

In contrast to the firmware, the software described in the book and provided on the website is much less developed. The examples of software drivers are enlightening, but they are a far cry from providing comprehensive applications. This shortcoming is deliberate, because the focus of the book is on firmware development. It is implied that the firmware will be then used to host some sort of an application or an operating system, whose development is outside the scope of the book. It is left to the reader to decide what this operating system will look like.

I conclude this short section by stressing that the FPro framework is one of few examples how a nontrivial and useful SOC can be composed from individual pieces, interconnected according to a simple and well defined protocol. The importance of these examples cannot be overstated. Development of software running on such a SOC is the principal challenge to be addressed by the book's audience.


We consider the FPro architecture as our prime candidate for the RiskFive SOC development. Thorough documentation, clearly defined rules, and well structured HDL code are the main assets of the FPro approach. Concerning the performance, 32-bit bus transactions executed at 100 MHz will provide sufficient bandwidth for a computer built around a single soft core such as MicroBlaze or RISC5.

The FPro bus may be less suited for a multicore system because FPro lacks bus arbitration. Our main challenge will be integration of the video framebuffer located in the DDR3 memory with the rest of the FPro SOC design. Placing the video framebuffer in the same RAM which is also accessed by the CPU will make the design inherently dual core, with one core being the CPU and the other being the video controller. It is not yet clear how such a dual core architecture can be supported by the the FPro bus.

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Updated Jan/26/2018.
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